The present invention relates to a method and an apparatus for identifying faulty address decoders belonging to function units which are connected via a common bus system connecting to a central control unit with a number of the function units, for safety reasons, being furnished with duplicated address decoders.
It is previously known from the U.S. Pat. No. 3,868,641, for example, to furnish function units with duplicated address decoders in order, thus, to achieve greater security against selection of an invalid unit. In said patent both decoders must operate simultaneously to give a reliable addressing indication. However, a decoder fault can show itself in such a manner that its detection is not obtained for the appropriate address or in such a manner that a detection is obtained for another or several other addresses. The fault can also be such that the decoder detects both the correct address and an invalid address. As long as only one of the decoders is impaired by a fault, erroneous selection is avoided because a signal is required from both of the decoders to insure that the associated function unit is actually addressed. Thus in case of no detection from one of the decoders the fault is immediately discovered as no response is obtained from the addressed unit. The apparatus of said patent can handle such faults. However when the fault is of that kind that an address is detected by a decoder which is not addressed, in addition to the decoders of the addressed function unit, it is necessary, however, to indicate the fault and its location in another way.